An important aim of ongoing research in the semiconductor industry is increasing semiconductor performance while decreasing the size of semiconductor devices. One known step the industry has taken to attain this increased semiconductor performance is to implement strained silicon technology. Fortunately, strained silicon technology allows for the formation of higher speed devices.
Strained-silicon transistors may be created a number of different ways, including by introducing a dislocation loop, or excess plane of atoms, into a crystalline material. In one instance strained layers are created by forming a layer of silicon germanium (SiGe) over or below a silicon epitaxial layer. The average distance between atoms in the SiGe crystal lattice is greater than the average distance between atoms in an ordinary silicon lattice. Because there is a natural tendency of atoms inside different crystals to align with one another when a second crystal is formed over a first crystal, when silicon is deposited on top of SiGe, or vice-versa, the silicon crystal lattice tends to stretch or “strain” to align the silicon atoms with the atoms in the SiGe layer. In another instance strained layers are created by a layer of dislocation loops. The insertion of an extra plane of atoms (a dislocation loop) in an ordinary silicon lattice creates stress in the surrounding silicon lattice. Fortunately, as the electrons in the strained silicon experience less resistance and flow up to 80% faster than in unstrained silicon, the introduction of the strained silicon layer allows for the formation of higher speed devices.
Problems currently exist, however, with the use of the strained silicon technology. One of the major problems occurs when the many smaller dislocation loops caused when forming the strained silicon tend to agglomerate into fewer but larger dislocation loops. Unfortunately, the larger dislocation loops, as compared to the smaller dislocation loops, have a tendency to penetrate to the surface of the device or cut across the junction, thus causing undesirable leaking through the p-n junction. Another problem exists when threading dislocations in the silicon-germanium layer grow toward the surface of the device rather than remaining where they are supposed to remain, or alternatively growing down. There is currently no feasible technique known for subsiding these aforementioned problems.
Accordingly, what is needed in the art is a semiconductor device and method of manufacture therefore that experiences the benefits of a strained silicon layer without experiencing the aforementioned drawbacks.